AI

The memory wall, part 2: GPU and CPU stacks work together to deliver Agentic AI

Jeremy Werner

Abstract visualization of glowing AI data streams and calculations

FMS 2026 | Part 2 of 4

Same brain, two memory systems

I used Part 1 to explain how agentic AI runs on two compute stacks, not one. The GPU reasons, generates and plans. The CPU orchestrates, acts and carries the plan out. Neither works without memory designed for its role.

There I highlighted the scale of the problem: context can grow into tens of terabytes under concurrency, while agentic workflows can drive infrastructure traffic to 100 times the traditional baseline. Now let’s look at how the reasoning stack manages KV cache, then at what the execution stack demands.

Five-tier KV cache hierarchy from near memory to networked KV lakes

Figure 1: Redefining the KV cache hierarchy. Source: IEEE Computer Society (journal article); IBM (technical paper).

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An optimized hierarchy for KV cache

The KV cache is not a location. It is a critical inference object that must be available to feed the next iteration of the decode pipeline. If it is retained, the system has to retrieve it quickly enough to keep inference moving. If it is discarded, the system has to recompute it, spending time, energy and compute to reproduce work it has already done. That makes KV cache placement a system-level design choice: what to keep, where to store it and when retrieval is more efficient than recomputation. Some systems may use as few as two storage tiers. The five-tier architecture shown here represents an optimized future state, with different capacity and retrieval-time tradeoffs at each level. Near memory, or HBM, holds the most active KV closest to the GPU. Main memory adds capacity for active context. Disaggregated memory pools larger working sets beyond the node. Context memory storage provides persistence with faster recall than recomputation. Networked KV lakes extend the hierarchy to exabytes of long-term context. Data center architects will configure their KV Cache tiers to optimize for their unique workload and application base and efficiency will come from placing KV cache in the right tier, at the right time, and orchestrating retrieval, eviction and recomputation optimally.

Four-tier agentic AI execution stack from main memory to networked data lakes

Figure 2: Executing agentic AI. Source: IBM; Red Hat; Databricks.

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Now the side that acts

Reasoning is only half the job. Agentic AI requires action, and that’s where the motor cortex takes over. Main memory supports operational execution: reasoning, generating and deciding in real time. Disaggregated memory can be used to extend the memory footprint to ensure CPU memory requirements don't outgrow the box, because we’d rather expand the system than underutilize it. Content memory storage lets applications pause and resume, and store local data persistantly. And networked data lakes provide the large scale storage required to source and store the data across the data center. An agent draws on all four tiers with every action while executing on the CPU. Similar memory and storage technologies appear across both stacks, but the pressure comes from different directions. The reasoning side must keep the decode pipeline fed. The execution side must preserve state and turn decisions into action. Both stacks drive the need for greater amounts of faster memory and storage.

Both stacks, every tier

That’s the architecture breaking down the memory wall: an optimized reasoning hierarchy that can scale to five tiers, alongside a four-tier execution stack. Not every system will implement every tier, and the optimal design will depend on workload scale, latency targets and the cost of retrieval versus recomputation. Design the hierarchy intentionally across both stacks, and the wall comes down. In Part 3, I’ll look at how Micron products are addressing the needs of the entire tier hierarchy of both stacks.

Senior Vice President & General Manager, Core Data Center Business Unit

Jeremy Werner

Jeremy Werner is Senior Vice President and General Manager of Micron’s Core Data Center Business Unit (CDBU), with P&L responsibility for Micron’s global core data center memory and storage business. He leads the business’s strategy, growth and execution across hyperscale, cloud, enterprise and OEM markets, positioning Micron to address the rapidly expanding memory and storage requirements of AI-driven data centers. Jeremy joined Micron in 2021 to lead the Storage Business Unit and was subsequently appointed to lead CDBU as the company expanded its focus on AI-driven growth.

Prior to Micron, Jeremy served as Senior Vice President and General Manager of KIOXIA America’s SSD business, where he led a multibillion-dollar business serving hyperscale, enterprise, data center and client markets. Earlier in his career, he held leadership roles across the memory and storage industry, including at SandForce/LSI, MetaRAM and Tidal Systems.

Jeremy earned a B.S. in Electrical Engineering from Cornell University and completed the Stanford Executive Program at Stanford Graduate School of Business. He is an inventor on more than 25 issued or pending patents and was recognized by JEDEC with a Chairman Award for his leadership in industry standardization.

Jeremy Werner

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