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The semiconductor ecosystem constitutes a highly intricate and interconnected framework encompassing various industries, technologies and institutions that facilitate the design, manufacturing, distribution and application of semiconductor devices. One segment of this framework — design and intellectual property (IP) providers — has experienced substantial evolution, establishing itself as an integral element in contemporary chip development.
With the advent of electronic design automation (EDA) tools in the 1980s and the growth of the semiconductor IP sector during the 1990s, system on a chip (SoC) designs have become increasingly dependent on reusable IP blocks. Presently, more than 80% of SoC content is comprised of reused IP, with a typical chip integrating more than 200 IP blocks.1
Introducing new technology within the semiconductor market presents considerable complexity. The degree of support from ecosystem partners — including IP providers and verification IP (VIP) software vendors — is often decisive, potentially inhibiting adoption or serving as a catalyst for commercial success.
The strategic collaboration between Micron and Cadence Design Systems signifies a notable milestone in memory technology advancement. This collaboration focuses on embedding direct link ECC protocol (DLEP) functionality within Cadence’s latest LPDDR5/5X memory controller IP, physical layer (PHY) IP and verification IP (VIP), facilitating substantial improvements in system performance across artificial intelligence, automotive and data center applications.
ECC data transfers with standard DRAM versus DRAM with DLEP
(click image to expand)
Importance of DLEP in memory technology
DLEP is a significant innovation designed to address the inherent constraints of traditional in-line error correction code (ECC). Its role is particularly critical for high-performance AI applications and high-reliability advanced driver assistance systems (ADAS) applications found in modern vehicles. A core advantage of DLEP is its capability to reclaim a significant proportion of payload memory space and bandwidth that would otherwise be allocated to in-line ECC overhead. This recovery underpins improved system performance and resource efficiency. Through the Micron-Cadence collaboration, these enhancements are fully realized.
DLEP represents a significant innovation aimed at addressing the limitations associated with traditional in-line ECC. This improvement is crucial for applications requiring high reliability and superior performance, such as AI accelerators and ADAS in automotive technologies.
Graph showing the 15% to 25% bandwidth increase between inline ECC and DLEP
(click image to expand)
One of the primary benefits of DLEP is its ability to recover a substantial percentage of payload memory space, a minimum 6% additional addressable memory space and bandwidth, a 15% to 25% bandwidth increase that would otherwise be sacrificed due to in-line ECC penalties. This recovery translates to improved system performance and greater efficiency, delivering approximately 10% lower power consumption on a pJ/b (picojoule-per-bit) perspective in memory management.2 The collaboration between Micron and Cadence ensures that these benefits are maximized.
Strategic collaboration for integration and verification
Micron's advanced DLEP functionality is seamlessly integrated into Cadence’s LPDDR5/5X IP portfolio and VIP tool suite. This integration is engineered to optimize the verification process for complex SoC designs, enabling the effective deployment of DLEP technology across diverse applications. VIP solutions are instrumental in authenticating the operation and efficacy of emerging memory technologies. The robust alliance between Micron and Cadence ensures that DLEP adoption establishes new standards in memory technology.
Cadence’s VIP toolset provides essential advantages such as thorough validation of complex SoC architectures, improved verification accuracy, fast time-to-market, cost reductions, and advanced capabilities like protocol compliance assessment and automated test generation, all of which contribute to the reliable and efficient deployment of new memory solutions. Cadence’s LPDDR5X VIP memory model3 supporting the DLEP feature allows for debug access to the additional memory cells used to store ECC, allows for callback overrides of the bit values on the fly while doing reads/writes, and checks for prohibited modes when DLEP is enabled.
This integrated approach helps to realize the benefits of DLEP technology, underpinning next-generation solutions.
DLEP advantages for AI and automotive
Integrating DLEP into memory architectures yields substantial benefits for AI, the automotive industry and other sectors seeking enhanced reliability, outstanding performance, data integrity and increased energy efficiency, which combine to extend the operational lifespan of mission-critical systems. Additionally, these advancements contribute to cost reduction, amplifying the value proposition of DLEP technology.
Advancing DLEP
The collaboration between Cadence and Micron is advancing the adoption of DLEP, enabling system designers to achieve higher bandwidth, improved memory utilization and lower power consumption — all while meeting stringent functional safety requirements. By integrating DLEP into Cadence’s LPDDR5/5X controller, PHY IP and VIP, engineers benefit from robust, silicon-proven solutions that streamline verification and accelerate time-to-market. As data-intensive and safety-critical workloads continue to grow, the collaboration of Cadence and Micron enables reliable, efficient memory performance for automotive, AI and beyond.
Learn more about Micron LPDDR5x solutions
Learn more about Cadence VIP simulation for LPDDR5x
1 LPDDR5X with enhanced ECC for automotive rises to the challenge | Micron Technology Inc. Measured against typical in-line system ECC schemes vs. DLEP
2 TRENDS IN INTELLECTUAL PROPERTY, Global Semiconductor Alliance Intellectual Property Interest Group
3 https://www.cadence.com/en_US/home/tools/system-design-and-verification/verification-ip/simulation-vip/memory-models/dram/lpddr5.html
