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Micron DDR5: Increased memory bandwidth transforming data into insight

By Brian Drake - 2020-03-31

As the ecosystem enabling DDR5 continues to develop, excitement grows. If you missed it, Micron announced early sampling of DDR5 in a press release on Jan. 6, 2020! Vice president and general manager of the Compute and Networking Business Unit, Tom Eby said it best, “Data center workloads will be increasingly challenged to extract value from the accelerating growth of data across virtually all applications. The key to enabling these workloads is higher-performance, denser, higher-quality memory.” He added, “Micron’s sampling of DDR5 RDIMMs represents a significant milestone, bringing the industry one step closer to unlocking the value in next-generation, data-centric applications.”


Multicore CPU architectures have continued to enable year-over-year compute performance gains. However, CPU core counts are increasing at a rate that surpasses that of total system memory bandwidth available. This unequal rate of increase actually results in bandwidth per CPU core declining. DDR4 has reached its maximum data rates and cannot continue to scale memory bandwidth with these ever-increasing core counts.

DDR5 to the rescue! DDR5 will offer greater than twice the effective bandwidth when compared to its predecessor DDR4, helping relieve this bandwidth per core crunch. DDR5 can deliver this due to fundamental DRAM architecture changes that do two things:

  1. Allow DRAM to be more efficient (less idle time on the data bus)
  2. Enable higher data rates

As available data continues to explode, it is exciting to ponder how this increased memory bandwidth, accompanied by increased compute power, will help answer today’s biggest questions in science and medicine, research and development, and smart manufacturing, to name just a few areas!

Check out the videos above that summarize the current system level memory bandwidth challenges as well as an introduction to DDR5. The problem statement and features that enable this potential have been discussed in previous blogs, white papers, and now a series of videos!

I also encourage you to visit micron.com regularly to see the most current content on DDR5 —the mainstream memory that delivers next-generation performance, scalability and total cost of ownership.

Brian Bradford

Brian Drake

Brian leverages 17 years of DRAM expertise to lead strategy development in the Data Center segment with a focus on enabling DDR5 solutions for hyperscale customers. Before moving to his current role within Micron Brian spent 6 years in Product Engineering where his time was split between leading and/or contributing to teams responsible for developing, enabling, and maintaining DRAM products. Four years prior to joining Micron, he held roles within Infineon and Qimonda as a DRAM test program engineer.